Identification of Spatial Fault Patterns in Semiconductor Wafers

Abstract

The semiconductor industry is constantly searching for new ways to increase the rate of both process development and yield learning. As more data is being collected and stored throughout the chip manufacturing process, it has become increasingly more difficult to analyze yield signals using traditional statistical methods. Most of the serious yield issues manifest themselves as non-random electrical failure maps. Our semi-supervised fault detection framework has elements of Spatial Signature Analysis (SSA) to capture yield signals for very large datasets without losing the critical details typically involved with summarization techniques. It includes signature detection, de-noising, clustering, and purification that allow one to create a true spatial response metric of the yield issue. Once this has been accomplished, one can load process data to join with the spatial response and invoke customized rule induction algorithms that generate a set of hypotheses - likely process causes for a specific spatial target response. The framework has been successfully used at Intel and represents an example of the growing influence of modern statistical learning in the semiconductor industry.

Speaker:

Dr. Eugene Tuv, Intel

Dr. Eugene Tuv is a Senior Staff Research Scientist in the Logic Technology Department at Intel. His research interests include supervised and unsupervised non-parametric machine learning with massive heterogeneous data. Prior to Intel he worked as a research scientist in the Institute of Nuclear Research, Ukrainian Academy of Science. He holds postgraduate degrees in Mathematics and Applied Statistics.