Draper Clock-Synchronization Protocol in SAL

In 1973, Daly, Hpokins, and McKenna (from Draper Lab.) presented a fault-tolerant digital clocking system at the FTCS conference. This is probably one of the first published system designs that is intended to tolerate arbitrary, asymmetric faults (i.e., Byzantine faults).

The following SAL models (05/14/2012) are two variant formalizations of this Draper Clock-Synchronization Protocol developed by Ashish Tiwari.

Data and Resources

Additional Info

Field Value
Maintainer Kevin Schweiker
Last Updated March 31, 2025, 14:53 (UTC)
Created March 31, 2025, 14:53 (UTC)
Identifier DASHLINK_600
Issued 2012-06-11
Modified 2020-01-29
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